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TSMC-Fab

ARM and TSMC have had a articulation understanding in place for several years to collaborate on R&D piece of work and early validation on procedure nodes, and they've announced a major milestone in that process. Equally of yesterday, ARM is announcing that it has successfully validated a new 10nm FinFET design at TSMC.

The unnamed multi-cadre test chip features a quad-core CPU from ARM, codenamed Artemis, a single-core GPU as a proof of concept, and the bit'southward interconnect and other various features.

Artemis-TestChip

This isn't an SoC that ARM will ever bring to market. Instead, information technology's purpose is to role as a validation tool and early reference pattern that helps both TSMC and ARM understand the specifics of the 10nm FinFET procedure as it moves towards commercial viability. One of the features that pure-play foundries like TSMC offer their customers are tools and libraries specifically designed to lucifer the capabilities of each process node. Since each new node has its own pattern rules and best practices, TSMC has to melody its offerings accordingly — and working with ARM to create a reasonably complex exam flake is a win/win situation for both companies. ARM gets early on insight into how best to tune upcoming Cortex processors; TSMC gets a standard architecture and SoC design that closely corresponds to the bodily chips information technology'll be building for its customers every bit the new process node moves into production.

ARM-10nm-vs-16nm

The slide above shows the gains TSMC expects to realize from moving to 10nm as opposed to its current 16nm procedure. To the best of our knowledge, TSMC's 10nm is a hybrid process, but it's not articulate exactly what that hybrid looks similar. Our current agreement is that the upcoming 10nm node would combine a 10nm FEOL (Forepart cease-of-line) with a 14nm BEOL (Dorsum-stop-of-line, which governs die size). EETimes, however, reported in March that TSMC's 10nm compress would retain a 20nm minimum feature size, while its 7nm would deliver a 14nm minimum characteristic size (10/twenty and seven/14, respectively). Either way, Intel is the only company that has announced a "true" 14nm or 10nm dice shrink. (The degree to which this process advantage materially helps Intel these days is open up to debate).

Two things to note: Get-go, the top line of the slide is potentially confusing. The 0.7x reduction of power would be easier to read if ARM had labeled it "ISO Performance at 0.7x power." 2nd, the performance gains predicted hither purely as a result of the node transition are downright anemic. I don't desire to read too much into these graphs because it's very early on days for 10nm, but there's been a lot of talk effectually 16/14nm equally a long-lived node, and results similar this are part of why — simply a handful of companies will desire to pay the actress costs for the boosted masks required as part of the die shrink. TSMC has already said that information technology believes 10nm will be a relatively short-lived node, and that information technology thinks it'll have more significant customer engagement for 7nm.

None of this means that ARM tin can't deliver compelling improvements at 10nm — only the limited amount of lithography improvements mean a heavier elevator for the CPU research teams and design staff, who need to observe boosted tricks they can utilize to clasp more performance out of silicon without driving upwards ability consumption.

As for when 10nm might ship, past timelines suggest it'll be a while nonetheless. TSMC has said it expects early 10nm tapeouts to drive sizeable need starting in Q2 2017. While that's a quick turn-around for a visitor whose 16nm only entered book production in August 2015, the speed could be explained if the 10nm node continues to leverage TSMC's existing 20nm technology. Bear in listen that in that location's a significant delay between when TSMC typically ships hardware and when consumer products launch, particularly in mobile devices where multiple companies perform complex verification procedures on multiple parts of the chip.

Either way, this tapeout is a meaning step forwards for both ARM and TSMC, and 10nm will evangelize improvements over the 16nm tech bachelor today.